AEC Papers

Selected Technical Papers

The following are technical papers related to AEC qualification test methods or various areas related to part quality/reliability and part-level testing philosophies:

An Investigation of Human Body Electrostatic Discharge (72KB) - This paper describes an investigation of the relationship between an ESD pulse from a real human body with that used in the various industry standard test methods.

Electro-Thermally Induced Parasitic Gate Leakage (GL) (176KB) - This is the first paper on the trapped charge phenomena which can occur in surface mounted plastic packaged parts (or during burn-in). This paper was the basis for the development of test method -006 in AEC - Q100.

The Effects of Materials and Post-Mold Profiles on Plastic Encapsulated Integrated Circuits (361KB) - This paper discusses the results of an investigation into the various factors effecting the trapped charge failure characteristics of plastic encapsulated integrated circuits. This paper is a continuation of the work performed in "Electro-Thermally Induced Parasitic Gate Leakage" and also supports test method -006 in AEC - Q100.

Wire Bonding - A Closer Look (645KB) - This paper discusses the work done to evaluate and improve the wire bonding process. It includes the work done with ball shear testing and the reasons that ball shear is far superior to wire pull for bond schedule development and quality monitoring.

A Comparison of Electrostatic Discharge Models and Failure Signatures for CMOS Integrated Circuit Devices (2,933KB) - This paper discusses the results of an ESD evaluation utilizing Human Body Model, Machine Model, and Field-Induced Charged Device Models on six different CMOS devices. It includes SEM photos of failure signatures for the various ESD models.

Investigation into Socketed CDM (SDM) Tester Parasitics (256KB) - This paper investigates the effects of tester background parasitics on the discharge waveform of an SDM tester.

New Latchup Mechanism in Complementary Bipolar Power ICs Triggered by Backside Die Attach Glue (220KB) This paper shows how latchup can occur due to a thyristor formed by the power transistor and glue die attach at the backside of the die.

Handling of Highly-Moisture-Sensitive Components – An Analysis of Low-Humidity Containment and Baking Scheduless (61KB) This paper presents a detailed analysis of how moisture is distributed in molded plastic packages and how the use of dry box storage and bake out effect the floor life of plastic packaged moisture sensitive surface mounted components. One point to note is that simply placing a part in a dry box does not stop the floor life clock. The primary author of this paper, Dr. R. L. Shook, is well know in the field of moisture sensitive surface mount components. He is the primary source for the technical data used to develop the IPC/JEDEC industry standards J-STD-020, and J-STD-033 on moisture sensitivity.

Developing a Transient-Induced Latch-up Standard for Integrated Circuits (358KB) This paper presents the results of a search for a more effective stimulus for assessing the latch-up susceptibility of integrated circuits. Different stimuli and amplitudes were found to have varying effectiveness in creating a latch-up event. The investigation also identified the inadequate response and recovery of existing test system power supplies and need for appropriate isolation techniques.

Issues Concerning CDM ESD Verification Modules – The Need to Move to Alumina (382KB) This paper presents the results of an evaluation of CDM waveform verification modules. These findings may provide the data for a new CDM test standard.

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